1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly to a DRAM (Dynamic Random Access Memory) having a stacked type capacitor.
2. Description of the Background Art
A DRAM is one of semiconductor memory devices allowing random input/output of stored information. Recently, the semiconductor technology, especially microprocessing technology have developed and, as a result, the degree of integration and storage capacity of the DRAM have been much increased.
As the degree of integration of a DRAM is increased, the area of a capacitor storing information (charges) has been decreased, resulting in erroneous reading of the stored memory content, or resulting in soft errors due to destruction of the stored content caused by .alpha. ray, for example.
As a method of solving such problems and to realize higher degree of integration and larger storage capacity, a memory cell including a so-called stacked type capacitor has been proposed, in which a capacitor is formed on a memory cell area, and a lower electrode of the capacitor is electrically connected to one electrode of a switching transistor formed on a semiconductor substrate, so as to substantially increase the area occupied by the capacitor.
FIGS. 9 to 11 show memory cells of a DRAM having conventional typical stacked type capacitors. Referring to these figures, a memory cell includes one transfer gate transistor portion and one stacked type capacitor portion. The transfer gate transistor portion includes a pair of source/drain regions 6 formed on a surface of a silicon substrate 1, and a word line 4 serving as a transfer gate, formed on the surface of silicon substrate 1 with an insulating film posed therebetween. The stacked type capacitor portion includes a storage node (lower electrode) 11 extending from above word line 4 to above a field insulating film 2 with a portion thereof connected to one side of source/drain regions 6, a dielectric layer 12 formed on the surface of storage node 11, and a cell plate (upper electrode) formed on the surface of the dielectric layer 12. Further, a bit line 15 is formed above the capacitor, with an interlayer insulating film 20 posed therebetween. Bit line 15 is connected to the other one of source/drain regions 6 of the transfer gate transistor through a bit line contact 16. The feature of the stacked type capacitor is that as the main portion of the capacitor extends above the gate electrode and the field insulating film, opposing area between capacitor electrodes is increased so that desired capacitor capacitance is ensured.
Recently, one such stacked type capacitor, in which the opposing area of the upper and lower electrodes of the capacitor is further increased by extending the main portion of the capacitor further to a portion above the bit line contact with the lower electrode of the capacitor positioned above the bit line, has been proposed, as the element has been more and more miniaturized in accordance with the higher degree of integration (for example, see 1990 Symposium on VLSI Technology, p. 13, or Japanese Patent Laying-Open No. 5-29579).
FIGS. 12 and 14 are typical plan views of memory cells in which such capacitor portions are formed above the bit lines, and FIG. 13 is a cross section taken along the line XIII--XIII of FIG. 12. Two common features of these examples are as follows.
(1) A storage node contact 17 which is a lower electrode contact of the capacitor is formed in each space surrounded by word lines 4 and bit lines 15.
(2) An active region 2a is arranged diagonally with respect to word lines 4 so that storage contact 17 of (1) above and a bit line contact 16 serve as source/drain regions.
The pitch of the word lines and the pitch of the bit lines are designed to be approximately equal, in order to arrange memory cells with highest density.
However, the following problems arise when the degree of integration and storage capacity of the DRAM are to be increased by using the memory cells having the capacitor portion formed above the bit line as in the above described prior art.
(1) Increased Leak Between Memory Cells
As the elements are miniaturized in accordance with higher degree of integration, the space between adjacent active regions comes to be narrower and narrower, and as a result, the field oxide film comes to have lower isolation capability. Especially between adjacent active regions where storage node contacts are arranged with the minimum pitch which is approximately the same as that of the word lines, the isolation becomes inferior to that in active regions where there is no storage node contact. This is caused by diffusion of impurities contained in the storage node into active regions through a storage node contact, and by undesired scraping of end portions of the field oxide film when the contact hole for the storage node contact is provided by etching, due to inaccuracy in registration.
(2) Inaccuracy in Registration of Storage Node and Storage Node Contact
In such a memory cell that has the capacitor portion provided above the bit line, the depth from the storage node to the active region (source/drain region) becomes longer than in a structure in which the capacitor portion is provided below, since the bit line and the interlayer insulating film above the bit line, as well as the word line and the interlayer insulating film above the word line are stacked on the lower side of the storage node. Therefore, when a contact hole for providing the storage node contact is to be opened, etching must be effected for a longer period of time. At the time of etching the contact hole for the storage node contact, the opening diameter of the contact hole must be larger at the upper portion than the bottom portion in order to provide a desired contact resistance at the bottom portion of the contact hole. For this reason, registration margin in the step of forming a storage node subsequent to the formation of the storage node contact is made very severe. If the storage node contact happens to be off the storage node region because of inaccuracy in registration of the storage node pattern, the inside of the storage node contact may also be etched when the storage node is patterned by etching, resulting in increased contact resistance. If the substrate itself is further scraped by undesired etching, rapid increase in junction leak may result, lowering reliability.
(3) Short-Circuit Between Storage Node Contact and Bit Line
If a storage node contact is opened tapered widely as mentioned in (2) above, there would be high possibility of short-circuit between the bit line formed above the word line and the storage node contact, resulting in lower production yield.
FIG. 15 shows an example of a conventional DRAM memory cell which has been proposed as solving the above described prior art problems. The planar layout of the conventional memory cell is shown in 1993 Symposium on VLSI Circuits, pp. 91-92.
In the prior art example shown in FIG. 15, the pitch of word lines 4 and the pitch of bit lines 15 satisfy the ratio of 2:3, and in each of rectangular regions surrounded by word lines 4 and bit lines 15, one storage node contact 17 is positioned. In this planar layout, distance between centers of storage node contacts 17 adjacent in the lateral direction (D in FIG. 15) is larger than the pitch 2 F of the word lines 4. However, minimum distance between centers of storage node contacts 17 adjacent in the longitudinal direction, and the distance between centers of a bit line contact 16 and nearest storage contact 17 are both approximately equal to the pitch 2 F of word lines 4. Therefore, even in the planar layout of the prior art example shown in FIG. 15, the distance between centers of contacts is not sufficient, failing to provide sufficient isolation between adjacent active regions 11.
Here, the letter F used for representing the distance between centers of contacts and pitch of word lines 4 or bit lines 15 is generally referred to as "feature size", which is minimum processable size in the design rule plus registration margin.